1. Field of the Invention
The present invention relates generally to integrated circuit protection devices and in particular to circuits for preventing damage to MOS integrated circuits by electrostatic discharge (ESD).
2. Description of Related Art
Integrated circuits utilizing MOS (metal oxide semiconductor) transistors are vulnerable to electrostatic discharge (ESD) induced failures, particularly transistors which are part of the integrated circuit interface circuitry connected to the external pins/pads of the circuit. Various standards have been developed to measure the tolerance of an integrated circuit to ESD. One such standard is the HBM (Human Body Model) military specification (MIL-STD-883D, Method 3015.7) intended to simulate the effects of ESD produced by a human which comes into contact with the pins of an integrated circuit. The so-called 2 KV HBM stress test generally calls for a capacitor of 100 pF to be charged to 2 KV. The capacitor is connected in series with a 1.5 k.OMEGA. resistor to simulate the impedance of a human body and the series circuit is connected across any two pins of the integrated circuit. The remaining pins of the integrated circuit under test are left unconnected. The resultant high voltage across the two pins will invariably result in a current flow through the integrated circuit on the order of 1.3 amperes, most of which flows in a period of less than 150 nanoseconds. In order to comply with the standard, the integrated circuit must be capable of enduring the test without permanent failure.
Various attempts have been made to provide circuitry associated with the integrated circuit interface pads to prevent damage due to ESD. One technique for providing a degree of protection is to connect an NMOS transistor having a grounded gate between the interface pads and the circuit common. Referring to the drawings, FIG. 1 shows a metal pad 10 which functions as one of the outputs of an integrated circuit. NMOS transistor 12 represents a portion of an output circuit of the integrated circuit. The drain of transistor 12 is connected to receive an input In which is to be buffered by the output circuit. In some application, a PMOS transistor (not depicted) may be connected between the output pad 10 and the positive supply voltage V.sub.CC to act as a pull-up. In other applications, the drain of transistor 12 is left unconnected, with the pull-up function being performed by circuitry external to the integrated circuit. This is sometimes referred to as an open-drain output.
FIG. 1 further includes a grounded gate NMOS transistor, generally designated by the numeral 14, connected between the pad 10 and the circuit common (or most negative voltage applied to the integrated circuit) V.sub.SS. Protection transistor 14, which is depicted in a simplified cross-sectional view, is formed in a P-type substrate with an overlying P type epitaxial (epi) region. An N+ diffusion 20 in epi 18 functions as the drain, with N region 20A forming a lightly doped section of the drain. A second N+ diffusion 22 functions as the source, with N region 22A forming a lightly doped section of the source. The area 18A intermediate the drain and source is the channel region of the transistor. A polysilicon gate 30 is disposed over the channel region 18A. In addition, a P+ region 32 is included for providing a contact to the transistor body (epi 18). As can be seen from FIG. 1, the drain 20 of protection transistor 14 is connected to the output pad 10, with the gate, source and body being connected to V.sub.SS.
Under normal operating conditions where power is applied to the power rails of the integrated circuit, the voltage at pad 10 is permitted to vary between the positive supply voltage V.sub.CC and V.sub.SS. NMOS protection transistor 14 will remain off due to the grounded gate 30. Output transistor 12 is thus free to drive the output pad 10 in response to changes in signal In.
When the integrated circuit is to be subjected to an ESD stress test, all connections to the integrated circuit, including the power connections, are removed. The simulated ESD voltage, such as is generated in the above-described HBM test, is applied to pad 10 which is positive with respect to V.sub.SS. This will cause the drain-source voltage of protection transistor 14 to rapidly increase to a value significantly larger than the normal positive supply voltage V.sub.CC.
FIG. 2 is a graph 34 illustrating the relationship between the drain-source voltage V.sub.DS and the drain-source current I.sub.DS of transistor 14. The large drain voltage operates to increase the reverse bias on the PN junction formed between N-type drain 20 and the P-type epi 18. At voltage V.sub.t1, the reversed biased junction undergoes avalanche breakdown which results in a drain-source current flow of I.sub.t1. The additional electron-hole pairs created by the breakdown cause the potential of the epi 18 to rise until the PN junction between the channel region 18A and the source region 22 becomes forward biased. This causes a parasitic lateral NPN bipolar transistor to conduct, with the drain 20 functioning as the collector, the channel region 18A of the epi acting as the base and the source region functioning as the emitter. The base current of the parasitic transistor is supplied by holes generated by impact ionization in the channel region 18A near drain 20A.
The conductive action of the parasitic NPN transistor causes voltage V.sub.DS to drop as indicated by graph section 34A of the FIG. 2 graph. This action is sometimes referred to as snap-back where the circuit exhibits negative resistance. If current I.sub.DS is permitted to increase, a second breakdown will occur at a drain-source voltage of V.sub.t2 which causes a drain-source current to increase to I.sub.t2. The second breakdown is a result of thermal runaway which usually operates to permanently damage the transistor. However, if the transistor remains in a region less than I.sub.t2, as indicated by graph section 34B, no permanent damage will be sustained.
In order to increase the level of current I.sub.t2 at which point thermal runaway occurs, transistor 14 is typically configured to have a large channel width W compared to the width of the channel of transistor 12. This is achieved by implementing transistor 14 in a large number of segments (fingers), with each segment being a single MOS transistor. The respective drain, source and gates of each of the N segments of W width are connected together to form a single transistor having an effective channel width of N*W. When the transistor 14 is operating in the avalanche mode (graph section 34B), the current is ideally distributed equally among the various transistor segments thereby reducing the likelihood of localized overheating that results in thermal runaway and the attendant secondary breakdown.
One disadvantage of the above-described approach is that under certain conditions, the ESD current will be split between the output transistor 12 and the protection transistor 14. Transistor 12 will usually be a relatively small device compared to transistor 14 and will have a typical maximum current capability of less than 10 milliamperes, with the maximum peak current being significantly higher. The ESD current will be in excess of 1.3 Amperes in accordance with the 2 KV Human Body Model specification. Thus, if the small transistor 12 is allowed to carry a too large a portion of the total ESD current, the transistor could be permanently damaged.
One prior art approach to address the problem is to insert a fixed resistance (not depicted) between the gate 30 and source 22 of transistor 14 as described in U.S. Pat. No. 5,615,073. When positive going ESD event occurs on pad 10, capacitive coupling between the drain and gate causes the gate voltage to increase. Since there is a substantially linear relationship between the drain current of a transistor and the impact ionization current which affects the operation of the parasitic NPN transistor, the increased gate voltage causes the avalanche breakdown voltage V.sub.t1 (FIG. 2) to decrease below the magnitude of the secondary breakdown voltage V.sub.t2. Protection from ESD is increased by lowering V.sub.t1 to a value below V.sub.t2 so that thermal runaway occurs at a higher magnitude of ESD voltage. A clamp transistor (not depicted) is connected in parallel with the resistor of the prior art protection circuit to limit the gate voltage to a maximum value.
Although the above-described prior art protection circuitry provides a significant improvement over no protection at all, it has been found that a small number of integrated circuits using the protection circuitry will not pass the 2 KV HBM stress test. In those cases, current flow will be divided between the large transistor 14 and the small transistor 12 such that the small transistor will be forced to carry an excessive amount of current for any given value of resistance connected between the gate and source of transistor 14.
The present invention provides a further improvement in ESD protection over the above-described approaches. Reliable protection is provided without adding significantly to the complexity of the integrated circuit. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.